Commit Graph

14 Commits

Author SHA1 Message Date
564a8fc68b Pulled interrupts into an optional module. 2023-07-08 11:57:20 -07:00
fc7175d488 Pull RMT into an optional module, refactor. 2023-07-08 10:21:13 -07:00
7b74cddf2d More module decomposition.
Needs much more on device testing.
2023-07-05 22:58:03 -07:00
fe87f1574c Adding platform detection opcodes + fix assembler bug.
Adding flags to allow runtime detection of different esp32 models,
riscv vs xtensa, and psram.

Use this to conditionally compile hook for relevant assemblers.
2023-01-21 21:27:29 -08:00
d78953151a Tweaking include order to avoid b0, b1, etc. macro clash, bump version. 2023-01-14 23:14:01 -08:00
2f79192ea0 Refactor fault handling. 2023-01-14 22:28:38 -08:00
600e82d67e Add fault handling for ESP32, ESP32-S2, and ESP32-S3.
Also bump the version.
2023-01-04 21:45:26 -08:00
1c500c2233 Simplify terminate + bye + fix build. 2022-12-31 21:02:04 -08:00
e69c1dba0c WIP Xtensa Assembler/Disassembler. 2022-10-21 20:07:26 -07:00
8bed92bef9 Start of adding code word support. 2022-09-04 16:58:11 -07:00
09fb5b9bb9 Restructure more to allow tiers. 2022-07-13 21:31:01 -07:00
9d874a08fb Replaced XV with Z to make things uniform + fixed remaining non-valid asm.js. 2022-07-12 18:13:56 -07:00
4cc02ffc96 Automate g_sys structure handling for web. 2022-07-10 21:25:22 -07:00
fb47179999 Re-root site. 2022-02-27 20:59:19 -08:00