310 lines
14 KiB
Forth
310 lines
14 KiB
Forth
\ Copyright 2022 Bradley D. Nelson
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\
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\ Licensed under the Apache License, Version 2.0 (the "License");
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\ you may not use this file except in compliance with the License.
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\ You may obtain a copy of the License at
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\
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\ http://www.apache.org/licenses/LICENSE-2.0
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\
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\ Unless required by applicable law or agreed to in writing, software
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\ distributed under the License is distributed on an "AS IS" BASIS,
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\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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\ See the License for the specific language governing permissions and
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\ limitations under the License.
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( Lazy loaded xtensa assembler )
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: xtensa-assembler r|
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current @
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also assembler definitions
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vocabulary xtensa xtensa definitions
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16 names a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
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: nop ;
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: reg. ( n -- ) base @ >r decimal ." a" . r> base ! ;
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: register ( -- in print ) ['] nop ['] reg. ;
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: numeric ( -- in print ) ['] nop ['] . ;
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numeric operand im
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: imm4 im im im im ;
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: imm8 imm4 imm4 ;
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: imm16 imm8 imm8 ;
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: sr imm8 ;
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( Offsets for J and branches )
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: >ofs ( n -- n ) chere - 4 - ;
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: ofs8. ( n -- ) 8 sextend address @ + 4 + . ;
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: ofs12. ( n -- ) 12 sextend address @ + 4 + . ;
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: ofs18. ( n -- ) 18 sextend address @ + 4 + . ;
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' >ofs ' ofs8. operand ofs8
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' >ofs ' ofs12. operand ofs12
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' >ofs ' ofs18. operand ofs18
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: offset8 8 for aft ofs8 then next ;
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: offset12 12 for aft ofs12 then next ;
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: offset18 18 for aft ofs18 then next ;
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( Offsets for CALL* )
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: >cofs ( n -- n ) chere - 2 rshift 1- ;
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: cofs. ( n -- ) 18 sextend 1+ 2 lshift address @ 3 invert and + . ;
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' >cofs ' cofs. operand cofs
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: coffset18 18 for aft cofs then next ;
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( Frame size of ENTRY )
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: >entry12 ( n -- n ) 3 rshift ;
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: entry12. ( n -- ) 3 lshift . ;
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' >entry12 ' entry12. operand entry12'
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: entry12 12 for aft entry12' then next ;
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: >sa ( n -- n ) 32 swap - ;
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: sa. ( n -- ) 32 swap - . ;
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' >sa ' sa. operand sa
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numeric operand x : xxxx x x x x ;
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numeric operand i : iiii i i i i ;
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numeric operand w
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numeric operand y
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numeric operand b : bbbb b b b b ;
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register operand r : rrrr r r r r ;
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register operand s : ssss s s s s ;
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register operand t : tttt t t t t ;
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imm4 ssss tttt l o o o OP L32I.N,
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imm4 ssss tttt l o o l OP S32I.N,
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rrrr ssss tttt l o l o OP ADD.N,
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rrrr ssss imm4 l o l l OP ADDI.N,
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iiii ssss l o i i l l o o OP BEQZ.N,
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iiii ssss l l i i l l o o OP BNEZ.N,
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iiii ssss o i i i l l o o OP MOVI.N,
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o o o o ssss tttt l l o l OP MOV.N,
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l l l l ssss o o l o l l o l OP BREAK.N,
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l l l l o o o o o o o o l l o l OP RET.N,
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l l l l o o o o o o o l l l o l OP RETW.N,
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l l l l o o o o o o l l l l o l OP NOP.N,
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l l l l o o o o o l l o l l o l OP ILL.N,
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o o o o o o o o o o o o o o o o o o o o o o o o OP ILL,
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o o o o o o o o o o o o o o o o l o o o o o o o OP RET,
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o o o o o o o o o o o o o o o o l o o l o o o o OP RETW,
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o o o o o o o o o o l o o o o o o o o o o o o o OP ISYNC,
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o o o o o o o o o o l o o o o o o o o l o o o o OP RSYNC,
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o o o o o o o o o o l o o o o o o o l o o o o o OP ESYNC,
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o o o o o o o o o o l o o o o o o o l l o o o o OP DSYNC,
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o o o o o o o o o o l o o o o o l o o o o o o o OP EXCW,
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o o o o o o o o o o l o o o o o l l o o o o o o OP MEMW,
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o o o o o o o o o o l o o o o o l l o l o o o o OP EXTW,
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o o o o o o o o o o l o o o o o l l l l o o o o OP NOP,
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o o o o o o o o o o l l o o o o o o o o o o o o OP RFE,
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o o o o o o o o o o l l o o o o o o l o o o o o OP RFME,
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o o o o o o o o o o l l o o o l o o o o o o o o OP RFUE,
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o o o o o o o o o o l l o o l o o o o o o o o o OP RFDE,
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o o o o o o o o o o l l o l o o o o o o o o o o OP RFWO,
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o o o o o o o o o o l l o l o l o o o o o o o o OP RFWU,
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o o o o o o o o o l o l o o o o o o o o o o o o OP SYSCALL,
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o o o o o o o o o l o l o o o l o o o o o o o o OP SIMCALL,
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l l l l o o o l l l l o o o o s o o o l o o o o OP RFDD,
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l l l l o o o l l l l o o o o o o o o o o o o o OP RFDO,
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o l l o o o o o rrrr o o o o tttt o o o o OP NEG,
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o l l o o o o o rrrr o o o l tttt o o o o OP ABS,
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o l l o o o o l sr tttt o o o o OP XSR,
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: ALU 4 bits o o o o rrrr ssss tttt o o o o OP ;
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$1 ALU AND, $2 ALU OR, $3 ALU XOR,
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( $6 ABS/NEG )
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$8 ALU ADD, $9 ALU ADDX2, $a ALU ADDX4, $b ALU ADDX8,
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$c ALU SUB, $d ALU SUBX2, $e ALU SUBX4, $f ALU SUBX8,
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: ANYALL o o o o o o o o l o 2 bits ssss tttt o o o o OP ;
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$0 ANYALL ANY4, $1 ANYALL ALL4, $2 ANYALL ANY8, $3 ANYALL ALL8,
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: ALU2 4 bits o o l o rrrr ssss tttt o o o o OP ;
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$0 ALU2 ANDB, $1 ALU2 ANDBC, $2 ALU2 ORB, $3 ALU2 ORBC,
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$4 ALU2 XORB,
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$8 ALU2 MULL, $a ALU2 MULUH, $b ALU2 MULSH,
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$c ALU2 QUOU, $d ALU2 QUOS, $e ALU2 REMU, $f ALU2 REMS,
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: BRANCH1 offset8 4 bits ssss tttt o l l l OP ;
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$0 BRANCH1 BNONE, $1 BRANCH1 BEQ, $2 BRANCH1 BLT, $3 BRANCH1 BLTU,
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$4 BRANCH1 BALL, $5 BRANCH1 BBC,
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offset8 o l l b ssss bbbb o l l l OP BBCI,
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$8 BRANCH1 BANY, $9 BRANCH1 BNE, $a BRANCH1 BGE, $b BRANCH1 BGEU,
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$c BRANCH1 BNALL, $d BRANCH1 BBS,
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offset8 l l l b ssss bbbb o l l l OP BBSI,
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: BRANCH2 offset12 ssss 4 bits o l l o OP ;
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: BRANCH2a offset8 rrrr ssss 4 bits o l l o OP ;
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: BRANCH2e entry12 ssss 4 bits o l l o OP ;
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( $0 J, ) $1 BRANCH2 BEQZ, $2 BRANCH2a BEQI, $3 BRANCH2e ENTRY,
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( $4 J, ) $5 BRANCH2 BNEZ, $6 BRANCH2a BNEI, ( BRANCH2b's )
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( $8 J, ) $9 BRANCH2 BLTZ, $a BRANCH2a BLTI, $b BRANCH2a BLTUI,
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( $c J, ) $d BRANCH2 BGEZ, $e BRANCH2a BGEI, $f BRANCH2a BGEUI,
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offset18 o o o l l o OP J,
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: BRANCH2b offset8 4 bits ssss o l l l o l l o OP ;
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$0 BRANCH2b BF, $1 BRANCH2b BT,
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$8 BRANCH2b LOOP, $9 BRANCH2b LOOPNEZ, $a BRANCH2b LOOPGTZ,
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: CALLOP coffset18 2 bits o l o l OP ;
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0 CALLOP CALL0, 1 CALLOP CALL4, 2 CALLOP CALL8, 3 CALLOP CALL12,
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: CALLXOP o o o o o o o o o o o o ssss l l 2 bits o o o o OP ;
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0 CALLXOP CALLX0, 1 CALLXOP CALLX4, 2 CALLXOP CALLX8, 3 CALLXOP CALLX12,
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o o o o o o o o o l o o ssss tttt o o o o OP BREAK,
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o o l l o o l l rrrr ssss tttt o o o o OP CLAMPS,
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: CACHING1 imm8 o l l l ssss 4 bits o o l o OP ;
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$0 CACHING1 DPFR, $1 CACHING1 DPFW, $2 CACHING1 DPFRO, $3 CACHING1 DPFWO,
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$4 CACHING1 DHWB, $5 CACHING1 DHWBI, $6 CACHING1 DHI, $7 CACHING1 DII,
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( $8 CACHING2 ) ( ?? ) ( ?? ) ( ?? )
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$c CACHING1 IPF, ( $d CACHING2 ) $e CACHING1 IHI, $f CACHING1 III,
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: CACHING2 imm4 4 bits o l l l ssss 4 bits o o l o OP ;
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$0 $8 CACHING2 DPFL, $2 $8 CACHING2 DHU, $3 $8 CACHING2 DIU,
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$4 $8 CACHING2 DIWB, $5 $8 CACHING2 DIWBI,
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$0 $d CACHING2 IPFL, $2 $d CACHING2 IHU, $3 $d CACHING2 IIU,
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iiii iiii l o l o iiii tttt o o l o OP MOVI,
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: LDSTORE imm8 4 bits ssss tttt o o l o OP ;
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$0 LDSTORE L8UI, $1 LDSTORE L16UI, $2 LDSTORE L32I, ( $3 CACHING )
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$4 LDSTORE S8I, $5 LDSTORE S16I, $6 LDSTORE S32I,
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$9 LDSTORE L16SI, ( $a MOVI ) $b LDSTORE L32AI,
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$c LDSTORE ADDI, $d LDSTORE ADDMI, $e LDSTORE S32C1I, $f LDSTORE S32RI,
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o l o o l o o l rrrr ssss tttt o o o o OP S32E,
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x x x x o l o sa rrrr sa sa sa sa tttt o o o o OP EXTUI,
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imm16 tttt o o o l OP L32R,
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l o o l o o o o o o w w ssss o o o o o l o o OP LDDEC,
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l o o o o o o o o o w w ssss o o o o o l o o OP LDINC,
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imm8 o o o o ssss tttt o o l l OP LSI,
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imm8 l o o o ssss tttt o o l l OP LSIU,
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o l o l o o o o l l o o ssss o o o o o o o o OP IDTLB,
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o l o l o o o o o l o o ssss o o o o o o o o OP IITLB,
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o o o o o o o o o o o o ssss l o l o o o o o OP JX,
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l l l l o o o l l o o o ssss tttt o o o o OP LDCT,
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l l l l o o o l o o o o ssss tttt o o o o OP LICT,
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l l l l o o o l o o l o ssss tttt o o o o OP LICW,
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o o o o l o o l rrrr ssss tttt o o o o OP L32E,
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o o o o l o o o rrrr ssss tttt o o o o OP LSX,
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o o o l l o o o rrrr ssss tttt o o o o OP LSXU,
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o o l o o o o o rrrr ssss tttt o o o o OP MOV,
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: CONDOP 4 bits o o l l rrrr ssss tttt o o o o OP ;
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$4 CONDOP MIN, $5 CONDOP MAX, $6 CONDOP MINU, $7 CONDOP MAXU,
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$8 CONDOP MOVEQZ, $9 CONDOP MOVNEZ, $a CONDOP MOVLTZ, $b CONDOP MOVGEZ,
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$c CONDOP MOVF,
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: ALU.S 4 bits l o l o rrrr ssss tttt o o o o OP ;
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$0 ALU.S ADD.S, $1 ALU.S SUB.S, $2 ALU.S MUL.S,
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$4 ALU.S MADD.S, $5 ALU.S MSUB.S,
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$8 ALU.S ROUND.S, $9 ALU.S TRUNC.S, $a ALU.S FLOOR.S, $b ALU.S CEIL.S,
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$c ALU.S FLOAT.S, $d ALU.S UFLOAT.S, $e ALU.S UTRUNC.S,
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: ALU2.S l l l l l o l o rrrr ssss 4 bits o o o o OP ;
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$0 ALU2.S MOV.S, $1 ALU2.S ABS.S,
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$4 ALU2.S RFR, $5 ALU2.S WFR, $6 ALU2.S NEG.S,
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: CMPSOP 4 bits l o l l rrrr ssss tttt o o o o OP ;
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$1 CMPSOP UN.S, $2 CMPSOP OEQ.S, $3 CMPSOP UEQ.S,
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$4 CMPSOP OLT.S, $5 CMPSOP ULT.S, $6 CMPSOP OLE.S, $7 CMPSOP ULE.S,
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$8 CMPSOP MOVEQZ.S, $9 CMPSOP MOVNEZ.S, $a CMPSOP MOVLTZ.S, $b CMPSOP MOVGEZ.S,
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$c CMPSOP MOVF.S, $d CMPSOP MOVT.S,
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o o o o o o o o o o o l ssss tttt o o o o OP MOVSP,
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l l o l o o l l rrrr ssss tttt o o o o OP MOVT,
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: MUL.AA o l l l o l 2 bits o o o o ssss tttt o l o o OP ;
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0 MUL.AA MUL.AA.LL, 1 MUL.AA MUL.AA.HL, 2 MUL.AA MUL.AA.LH, 3 MUL.AA MUL.AA.HH,
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: MUL.AD o l l l o l 2 bits o o o o ssss o y o o o l o o OP ;
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0 MUL.AD MUL.AD.LL, 1 MUL.AD MUL.AD.HL, 2 MUL.AD MUL.AD.LH, 3 MUL.AD MUL.AD.HH,
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: MUL.DA o l l o o l 2 bits o x o o o o o o tttt o l o o OP ;
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0 MUL.DA MUL.DA.LL, 1 MUL.DA MUL.DA.HL, 2 MUL.DA MUL.DA.LH, 3 MUL.DA MUL.DA.HH,
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: MUL.DD o o l o o l 2 bits o x o o o o o o o y o o o l o o OP ;
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0 MUL.DD MUL.DD.LL, 1 MUL.DD MUL.DD.HL, 2 MUL.DD MUL.DD.LH, 3 MUL.DD MUL.DD.HH,
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l l o l o o o l rrrr ssss tttt o o o o OP MUL16S,
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l l o o o o o l rrrr ssss tttt o o o o OP MUL16U,
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: MULA.AA o l l l l o 2 bits ssss tttt o l o o OP ;
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0 MULA.AA MULA.AA.LL, 1 MULA.AA MULA.AA.HL, 2 MULA.AA MULA.AA.LH, 3 MULA.AA MULA.AA.HH,
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: MULA.AD o o l l l o 2 bits ssss tttt o l o o OP ;
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0 MULA.AD MULA.AD.LL, 1 MULA.AD MULA.AD.HL, 2 MULA.AD MULA.AD.LH, 3 MULA.AD MULA.AD.HH,
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: MULA.DA o l l o l o 2 bits o x o o o o o o tttt o l o o OP ;
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0 MULA.DA MULA.DA.LL, 1 MULA.DA MULA.DA.HL, 2 MULA.DA MULA.DA.LH, 3 MULA.DA MULA.DA.HH,
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: MULA.DA.LDDEC o l o l l o 2 bits o x o o o o o o tttt o l o o OP ;
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0 MULA.DA.LDDEC MULA.DA.LL.LDDEC, 1 MULA.DA.LDDEC MULA.DA.HL.LDDEC,
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2 MULA.DA.LDDEC MULA.DA.LH.LDDEC, 3 MULA.DA.LDDEC MULA.DA.HH.LDDEC,
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: MULA.DA.LDINC o l o o l o 2 bits o x w o o o o o tttt o l o o OP ;
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0 MULA.DA.LDINC MULA.DA.LL.LDINC, 1 MULA.DA.LDINC MULA.DA.HL.LDINC,
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2 MULA.DA.LDINC MULA.DA.LH.LDINC, 3 MULA.DA.LDINC MULA.DA.HH.LDINC,
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: MULA.DD o o l o l o 2 bits o x o o o o o o o y o o o l o o OP ;
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0 MULA.DD MULA.DD.LL, 1 MULA.DD MULA.DD.HL, 2 MULA.DD MULA.DD.LH, 3 MULA.DD MULA.DD.HH,
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: MULA.DD.LDDEC o o o l l o 2 bits o x w w o o o o tttt o l o o OP ;
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0 MULA.DD.LDDEC MULA.DD.LL.LDDEC, 1 MULA.DD.LDDEC MULA.DD.HL.LDDEC,
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2 MULA.DD.LDDEC MULA.DD.LH.LDDEC, 3 MULA.DD.LDDEC MULA.DD.HH.LDDEC,
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: MULA.DD.LDINC o o o o l o 2 bits o x w w o o o o tttt o l o o OP ;
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0 MULA.DD.LDINC MULA.DD.LL.LDINC, 1 MULA.DD.LDINC MULA.DD.HL.LDINC,
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2 MULA.DD.LDINC MULA.DD.LH.LDINC, 3 MULA.DD.LDINC MULA.DD.HH.LDINC,
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: MULS.AA o l l l l o 2 bits o o o o ssss tttt o l o o OP ;
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0 MULS.AA MULA.AA.LL, 1 MULS.AA MULA.AA.HL, 2 MULS.AA MULA.AA.LH, 3 MULS.AA MULA.AA.HH,
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: MULS.AD o o l l l o 2 bits o o o o ssss o y o o o l o o OP ;
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0 MULS.AD MULA.AD.LL, 1 MULS.AD MULA.AD.HL, 2 MULS.AD MULA.AD.LH, 3 MULS.AD MULA.AD.HH,
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: MULS.DA o l l o l o 2 bits o x o o o o o o tttt o l o o OP ;
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0 MULS.DA MULA.DA.LL, 1 MULS.DA MULA.DA.HL, 2 MULS.DA MULA.DA.LH, 3 MULS.DA MULA.DA.HH,
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: MULS.DD o o l o l o 2 bits o x o o o o o o o y o o o l o o OP ;
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0 MULS.DD MULA.DD.LL, 1 MULS.DD MULA.DD.HL, 2 MULS.DD MULA.DD.LH, 3 MULS.DD MULA.DD.HH,
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o l o o o o o o l l l o ssss tttt o o o o OP NSA,
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o l o o o o o o l l l l ssss tttt o o o o OP NSAU,
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o l o l o o o o l l o l ssss tttt o o o o OP PDTLB,
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o l o l o o o o o l o l ssss tttt o o o o OP PITLB,
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o l o l o o o o l o l l ssss tttt o o o o OP RDTLB0,
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o l o l o o o o l l l l ssss tttt o o o o OP RDTLB1,
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o l o o o o o o o l l o ssss tttt o o o o OP RER,
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o l o l o o o o o o l l ssss tttt o o o o OP RITLB0,
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o l o l o o o o o l l l ssss tttt o o o o OP RITLB1,
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o l o o o o o o l o o o o o o o imm4 o o o o OP ROTW,
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o o o o o o o o o o l l imm4 o o o l o o o o OP RFI,
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o o o o o o o o o l l o imm4 tttt o o o o OP RSIL,
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o o o o o o l l sr tttt o o o o OP RSR,
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l l l o o o l l rrrr ssss tttt o o o o OP RUR,
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l l l l o o o l l o o l ssss tttt o o o o OP SDCT,
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o o l o o o l l rrrr ssss tttt o o o o OP SEXT,
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l l l l o o o l o o o l ssss tttt o o o o OP SICT,
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l l l l o o o l o o l l ssss tttt o o o o OP SICW,
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l o l o o o o l rrrr ssss o o o o o o o o OP SLL,
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o o o sa o o o l rrrr ssss sa sa sa sa o o o o OP SLLI,
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l o l l o o o l rrrr o o o o tttt o o o o OP SRA,
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o o l x o o o l rrrr xxxx tttt o o o o OP SRAI,
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l o o o o o o l rrrr ssss tttt o o o o OP SRC,
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l o o l o o o l rrrr o o o o tttt o o o o OP SRL,
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o l o o o o o l rrrr xxxx tttt o o o o OP SRLI,
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o l o o o o o o o o l l ssss o o o o o o o o OP SSA8B,
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o l o o o o o o o o l o ssss o o o o o o o o OP SSA8L,
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o l o o o o o o o l o o xxxx o o o x o o o o OP SSAI,
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imm8 o l o o ssss tttt o o l l OP SSI,
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imm8 l l o o ssss tttt o o l l OP SSIU,
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o l o o o o o o o o o l ssss o o o o o o o o OP SSL,
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o l o o o o o o o o o o ssss o o o o o o o o OP SSR,
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o l o o l o o o rrrr ssss tttt o o o o OP SSX,
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o l o l l o o o rrrr ssss tttt o o o o OP SSXU,
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( TODO: UMUL.AA.* )
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o o o o o o o o o l l l imm4 o o o o o o o o OP WAITI,
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o l o l o o o o l l l o ssss tttt o o o o OP WDTLB,
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o l o o o o o o o l l l ssss tttt o o o o OP WER,
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o l o l o o o o o l l o ssss tttt o o o o OP WITLB,
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o o o l o o l l sr tttt o o o o OP WSR,
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l l l l o o l l sr tttt o o o o OP WUR,
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also forth definitions
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: xtensa-assembler xtensa ;
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previous previous
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xtensa-assembler
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current !
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| evaluate ;
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[THEN]
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