Fix up optionals, pull out oled.
This commit is contained in:
Brad Nelson
21
esp32/optional/README-optional.txt
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21
esp32/optional/README-optional.txt
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@ -0,0 +1,21 @@
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+----------------------------------+
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| ESP32forth - Optional Packages |
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+----------------------------------+
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ESPforth supports a number of optional packages, included in this directory.
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By default ESPforth will only include core functionality.
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To include one or more of these modules, move them from this directory
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into the parent directory, next to the ESPforth.ino file.
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These are the current optional modules:
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* assemblers.h - Assemblers for ESP32 Xtensa and ESP32 RISC-V
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* oled.h - Support for the SSD1306 Oled
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Initially ESP32forth focused on a minimal C kernel, with most functionality
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built in Forth code loaded at boot. Eventually, as support for more capabilities
|
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were added to ESPforth, this became unsustainable.
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Optional modules demonstrate good patterns for use in your own extensions
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to ESP32forth. You can add you own modules by #including them from
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an optional userwords.h file placed next to ESPforth.ino
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45
esp32/optional/assemblers/assemblers.h
Normal file
45
esp32/optional/assemblers/assemblers.h
Normal file
@ -0,0 +1,45 @@
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/*
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* Copyright 2023 Bradley D. Nelson
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
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||||
* http://www.apache.org/licenses/LICENSE-2.0
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||||
*
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||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
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||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
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||||
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/*
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* ESP32forth Assemblers v{{VERSION}}
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* Revision: {{REVISION}}
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*/
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#define OPTIONAL_ASSEMBLERS_SUPPORT \
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XV(internals, "assembler-source", ASSEMBLER_SOURCE, \
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PUSH assembler_source; PUSH sizeof(assembler_source) - 1) \
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PLATFORM_ASSEMBLER_SUPPORT
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{{assembler}}
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#if defined(__riscv)
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# define PLATFORM_ASSEMBLER_SUPPORT \
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XV(internals, "riscv-assembler-source", RISCV_ASSEMBLER_SOURCE, \
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PUSH riscv_assembler_source; PUSH sizeof(riscv_assembler_source) - 1)
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{{riscv_assembler}}
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#else
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# define PLATFORM_ASSEMBLER_SUPPORT \
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XV(internals, "xtensa-assembler-source", XTENSA_ASSEMBLER_SOURCE, \
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PUSH xtensa_assembler_source; PUSH sizeof(xtensa_assembler_source) - 1)
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{{xtensa_assembler}}
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#endif
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154
esp32/optional/assemblers/riscv-assembler.fs
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154
esp32/optional/assemblers/riscv-assembler.fs
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@ -0,0 +1,154 @@
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\ Copyright 2022 Bradley D. Nelson
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\
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\ Licensed under the Apache License, Version 2.0 (the "License");
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\ you may not use this file except in compliance with the License.
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\ You may obtain a copy of the License at
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||||
\
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||||
\ http://www.apache.org/licenses/LICENSE-2.0
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\
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\ Unless required by applicable law or agreed to in writing, software
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||||
\ distributed under the License is distributed on an "AS IS" BASIS,
|
||||
\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
\ See the License for the specific language governing permissions and
|
||||
\ limitations under the License.
|
||||
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RISC-V? [IF]
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|
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( Lazy loaded RISC-V assembler )
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: riscv-assembler r|
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current @
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also assembler definitions
|
||||
vocabulary riscv riscv definitions
|
||||
|
||||
32 names zero x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31
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||||
: nop ;
|
||||
: reg. ( n -- ) dup if base @ >r decimal ." x" . r> base ! else drop ." zero " then ;
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: register ( -- in print ) ['] nop ['] reg. ;
|
||||
|
||||
: reg>reg' ( n -- n ) 8 - 7 and ;
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: reg'. ( n -- ) 8 + reg. ;
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||||
: register' ( -- in print ) ['] reg>reg' ['] reg'. ;
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||||
|
||||
: numeric ( -- in print ) ['] nop ['] . ;
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||||
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||||
numeric operand i : iiii i i i i ;
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||||
|
||||
( Offsets for JAL )
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||||
: >ofs ( n -- n ) chere - dup 20 rshift 1 and 31 12 - lshift
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over 1 rshift $3ff and 21 12 - lshift or
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over 11 rshift 1 and 20 12 - lshift or
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swap 12 rshift $ff and or ;
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: ofs. ( n -- ) dup 31 12 - rshift 1 and 20 lshift
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over 21 12 - rshift $3ff and 1 lshift or
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over 20 12 - rshift 1 and 11 lshift or
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swap $ff and 12 lshift or 21 sextend address @ + . ;
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||||
' >ofs ' ofs. operand ofs
|
||||
: offset 20 for aft ofs then next ;
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||||
|
||||
register operand rd# : rd rd# rd# rd# rd# rd# ;
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register' operand rd#' : rd' rd#' rd#' rd#' ;
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||||
register operand rs1# : rs1 rs1# rs1# rs1# rs1# rs1# ;
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register' operand rs1#' : rs1' rs1#' rs1#' rs1#' ;
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register operand rs2# : rs2 rs2# rs2# rs2# rs2# rs2# ;
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register' operand rs2#' : rs2' rs2#' rs2#' rs2#' ;
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||||
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: R-TYPE { fn7 fn3 opc }
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fn7 7 bits rs2 rs1 fn3 3 bits rd opc 7 bits OP ;
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: I-TYPE { fn3 opc }
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iiii iiii iiii rs1 fn3 3 bits rd opc 7 bits OP ;
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: S-TYPE { fn3 opc }
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iiii i i i rs2 rs1 fn3 3 bits i iiii opc 7 bits OP ;
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: B-TYPE { fn3 opc }
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iiii i i i rs2 rs1 fn3 3 bits i iiii opc 7 bits OP ;
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||||
: U-TYPE { opc }
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iiii iiii iiii iiii iiii rd opc 7 bits OP ;
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: J-TYPE { opc }
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offset rd opc 7 bits OP ;
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$37 U-TYPE LUI,
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$17 U-TYPE AUIPC,
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$6F J-TYPE JAL,
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$0 $67 I-TYPE JALR,
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$0 $63 B-TYPE BEQ, $1 $63 B-TYPE BNE,
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$4 $63 B-TYPE BLT, $5 $63 B-TYPE BGE,
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$6 $63 B-TYPE BLTU, $7 $63 B-TYPE BGEU,
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||||
|
||||
$0 $03 I-TYPE LB, $1 $03 I-TYPE LH, $2 $03 I-TYPE LW,
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||||
$4 $03 I-TYPE LBU, $5 $03 I-TYPE LHU,
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|
||||
$0 $23 S-TYPE SB, $1 $23 S-TYPE SH, $2 $23 S-TYPE SW,
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||||
|
||||
$0 $13 I-TYPE ADDI, $2 $13 I-TYPE SLTI, $3 $13 I-TYPE SLTIU,
|
||||
$4 $13 I-TYPE XORI, $6 $13 I-TYPE ORI, $7 $13 I-TYPE ANDI,
|
||||
|
||||
$00 $1 $13 R-TYPE SLLI,
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||||
$00 $5 $13 R-TYPE SRLI, $20 $5 $13 R-TYPE SRAI,
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||||
|
||||
$00 $0 $33 R-TYPE ADD, $20 $0 $33 R-TYPE SUB,
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||||
|
||||
$00 $1 $33 R-TYPE SLL, $00 $2 $33 R-TYPE SLT,
|
||||
$00 $3 $33 R-TYPE SLTU, $00 $4 $33 R-TYPE XOR,
|
||||
|
||||
$00 $5 $33 R-TYPE SRL, $20 $5 $33 R-TYPE SRA,
|
||||
|
||||
$00 $6 $33 R-TYPE OR, $20 $7 $33 R-TYPE AND,
|
||||
|
||||
( TODO FENCE, FENCE.I )
|
||||
|
||||
o o o o o o o o o o o o o o o o o o o o o o o o o o o o l l l l OP ECALL,
|
||||
o o o o o o o o o o o l o o o o o o o o o o o o o o o o l l l l OP EBREAK,
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||||
|
||||
( TODO CSR* )
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o o o o o o o o o o o o o o o o OP C.ILL,
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o o o i i i i i i i i rd' o o OP C.ADDI4SP,
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||||
o o l i i i rs1' i i rd' o o OP C.FLD,
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o l o i i i rs1' i i rd' o o OP C.LW,
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||||
o l l i i i rs1' i i rd' o o OP C.FLW,
|
||||
( 4 reserved )
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l o l i i i rs1' i i rd' o o OP C.FSD,
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l l o i i i rs1' i i rd' o o OP C.SW,
|
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l l l i i i rs1' i i rd' o o OP C.FSW,
|
||||
|
||||
o o o o o o o o o o o o o o o l OP C.NOP,
|
||||
o o o i rs1 i i i i i o l OP C.ADDI,
|
||||
o o l i i i i i i i i i i i o l OP C.JAL,
|
||||
o l o i rd i i i i i o l OP C.LI,
|
||||
o l l i rd i i i i i o l OP C.LUI,
|
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l o o i o o rs1' i i i i i o l OP C.SRLI,
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||||
l o o i o l rs1' i i i i i o l OP C.SRAI,
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l o o i l o rs1' i i i i i o l OP C.ANDI,
|
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l o o o l l rs1' o o rs2' o l OP C.SUB,
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l o o o l l rs1' o l rs2' o l OP C.XOR,
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l o o o l l rs1' l o rs2' o l OP C.OR,
|
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l o o o l l rs1' l l rs2' o l OP C.AND,
|
||||
l o o l l l rs1' o o rs2' o l OP C.SUBW,
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l o o l l l rs1' o l rs2' o l OP C.ADDW,
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||||
l o l i i i i i i i i i i i o l OP C.J,
|
||||
l l o i i i rs1' i i i i i o l OP BEQZ,
|
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l l l i i i rs1' i i i i i o l OP BNEZ,
|
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|
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o o o i rs1 i i i i i l o OP C.SLLI,
|
||||
o o l i rd i i i i i l o OP C.FLDSP,
|
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o l o i rd i i i i i l o OP C.LWSP,
|
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o l l i rd i i i i i l o OP C.FLWSP,
|
||||
l o o o rs1 o o o o o l o OP C.JR,
|
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l o o o rd rs2 l o OP C.MV,
|
||||
l o o l o o o o o o o o o o l o OP C.EBREAK,
|
||||
l o o l rs1 o o o o o l o OP C.JALR,
|
||||
l o o l rd rs2 l o OP C.ADD,
|
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l o l i i i i i i rs2 l o OP C.FSDSP,
|
||||
l l o i i i i i i rs2 l o OP C.SWSP,
|
||||
l l l i i i i i i rs2 l o OP C.FSWSP,
|
||||
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also forth definitions
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||||
: riscv-assembler riscv ;
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previous previous
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riscv-assembler
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current !
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||||
|
||||
| evaluate ;
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||||
|
||||
[THEN]
|
||||
311
esp32/optional/assemblers/xtensa-assembler.fs
Normal file
311
esp32/optional/assemblers/xtensa-assembler.fs
Normal file
@ -0,0 +1,311 @@
|
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\ Copyright 2022 Bradley D. Nelson
|
||||
\
|
||||
\ Licensed under the Apache License, Version 2.0 (the "License");
|
||||
\ you may not use this file except in compliance with the License.
|
||||
\ You may obtain a copy of the License at
|
||||
\
|
||||
\ http://www.apache.org/licenses/LICENSE-2.0
|
||||
\
|
||||
\ Unless required by applicable law or agreed to in writing, software
|
||||
\ distributed under the License is distributed on an "AS IS" BASIS,
|
||||
\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
\ See the License for the specific language governing permissions and
|
||||
\ limitations under the License.
|
||||
|
||||
Xtensa? [IF]
|
||||
|
||||
( Lazy loaded xtensa assembler )
|
||||
: xtensa-assembler r|
|
||||
|
||||
current @
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also assembler definitions
|
||||
vocabulary xtensa xtensa definitions
|
||||
|
||||
16 names a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
|
||||
: nop ;
|
||||
: reg. ( n -- ) base @ >r decimal ." a" . r> base ! ;
|
||||
: register ( -- in print ) ['] nop ['] reg. ;
|
||||
: numeric ( -- in print ) ['] nop ['] . ;
|
||||
|
||||
numeric operand im
|
||||
: imm4 im im im im ;
|
||||
: imm8 imm4 imm4 ;
|
||||
: imm16 imm8 imm8 ;
|
||||
: sr imm8 ;
|
||||
|
||||
( Offsets for J and branches )
|
||||
: >ofs ( n -- n ) chere - 4 - ;
|
||||
: ofs8. ( n -- ) 8 sextend address @ + 4 + . ;
|
||||
: ofs12. ( n -- ) 12 sextend address @ + 4 + . ;
|
||||
: ofs18. ( n -- ) 18 sextend address @ + 4 + . ;
|
||||
' >ofs ' ofs8. operand ofs8
|
||||
' >ofs ' ofs12. operand ofs12
|
||||
' >ofs ' ofs18. operand ofs18
|
||||
: offset8 8 for aft ofs8 then next ;
|
||||
: offset12 12 for aft ofs12 then next ;
|
||||
: offset18 18 for aft ofs18 then next ;
|
||||
|
||||
( Offsets for CALL* )
|
||||
: >cofs ( n -- n ) chere - 2 rshift 1- ;
|
||||
: cofs. ( n -- ) 18 sextend 1+ 2 lshift address @ 3 invert and + . ;
|
||||
' >cofs ' cofs. operand cofs
|
||||
: coffset18 18 for aft cofs then next ;
|
||||
|
||||
( Frame size of ENTRY )
|
||||
: >entry12 ( n -- n ) 3 rshift ;
|
||||
: entry12. ( n -- ) 3 lshift . ;
|
||||
' >entry12 ' entry12. operand entry12'
|
||||
: entry12 12 for aft entry12' then next ;
|
||||
|
||||
: >sa ( n -- n ) 32 swap - ;
|
||||
: sa. ( n -- ) 32 swap - . ;
|
||||
' >sa ' sa. operand sa
|
||||
|
||||
numeric operand x : xxxx x x x x ;
|
||||
numeric operand i : iiii i i i i ;
|
||||
numeric operand w
|
||||
numeric operand y
|
||||
numeric operand b : bbbb b b b b ;
|
||||
|
||||
register operand r : rrrr r r r r ;
|
||||
register operand s : ssss s s s s ;
|
||||
register operand t : tttt t t t t ;
|
||||
|
||||
imm4 ssss tttt l o o o OP L32I.N,
|
||||
imm4 ssss tttt l o o l OP S32I.N,
|
||||
rrrr ssss tttt l o l o OP ADD.N,
|
||||
rrrr ssss imm4 l o l l OP ADDI.N,
|
||||
iiii ssss l o i i l l o o OP BEQZ.N,
|
||||
iiii ssss l l i i l l o o OP BNEZ.N,
|
||||
iiii ssss o i i i l l o o OP MOVI.N,
|
||||
o o o o ssss tttt l l o l OP MOV.N,
|
||||
l l l l ssss o o l o l l o l OP BREAK.N,
|
||||
l l l l o o o o o o o o l l o l OP RET.N,
|
||||
l l l l o o o o o o o l l l o l OP RETW.N,
|
||||
l l l l o o o o o o l l l l o l OP NOP.N,
|
||||
l l l l o o o o o l l o l l o l OP ILL.N,
|
||||
|
||||
o o o o o o o o o o o o o o o o o o o o o o o o OP ILL,
|
||||
o o o o o o o o o o o o o o o o l o o o o o o o OP RET,
|
||||
o o o o o o o o o o o o o o o o l o o l o o o o OP RETW,
|
||||
o o o o o o o o o o l o o o o o o o o o o o o o OP ISYNC,
|
||||
o o o o o o o o o o l o o o o o o o o l o o o o OP RSYNC,
|
||||
o o o o o o o o o o l o o o o o o o l o o o o o OP ESYNC,
|
||||
o o o o o o o o o o l o o o o o o o l l o o o o OP DSYNC,
|
||||
o o o o o o o o o o l o o o o o l o o o o o o o OP EXCW,
|
||||
o o o o o o o o o o l o o o o o l l o o o o o o OP MEMW,
|
||||
o o o o o o o o o o l o o o o o l l o l o o o o OP EXTW,
|
||||
o o o o o o o o o o l o o o o o l l l l o o o o OP NOP,
|
||||
o o o o o o o o o o l l o o o o o o o o o o o o OP RFE,
|
||||
o o o o o o o o o o l l o o o o o o l o o o o o OP RFME,
|
||||
o o o o o o o o o o l l o o o l o o o o o o o o OP RFUE,
|
||||
o o o o o o o o o o l l o o l o o o o o o o o o OP RFDE,
|
||||
o o o o o o o o o o l l o l o o o o o o o o o o OP RFWO,
|
||||
o o o o o o o o o o l l o l o l o o o o o o o o OP RFWU,
|
||||
o o o o o o o o o l o l o o o o o o o o o o o o OP SYSCALL,
|
||||
o o o o o o o o o l o l o o o l o o o o o o o o OP SIMCALL,
|
||||
l l l l o o o l l l l o o o o s o o o l o o o o OP RFDD,
|
||||
l l l l o o o l l l l o o o o o o o o o o o o o OP RFDO,
|
||||
|
||||
o l l o o o o o rrrr o o o o tttt o o o o OP NEG,
|
||||
o l l o o o o o rrrr o o o l tttt o o o o OP ABS,
|
||||
o l l o o o o l sr tttt o o o o OP XSR,
|
||||
|
||||
: ALU 4 bits o o o o rrrr ssss tttt o o o o OP ;
|
||||
$1 ALU AND, $2 ALU OR, $3 ALU XOR,
|
||||
( $6 ABS/NEG )
|
||||
$8 ALU ADD, $9 ALU ADDX2, $a ALU ADDX4, $b ALU ADDX8,
|
||||
$c ALU SUB, $d ALU SUBX2, $e ALU SUBX4, $f ALU SUBX8,
|
||||
|
||||
: ANYALL o o o o o o o o l o 2 bits ssss tttt o o o o OP ;
|
||||
$0 ANYALL ANY4, $1 ANYALL ALL4, $2 ANYALL ANY8, $3 ANYALL ALL8,
|
||||
|
||||
: ALU2 4 bits o o l o rrrr ssss tttt o o o o OP ;
|
||||
$0 ALU2 ANDB, $1 ALU2 ANDBC, $2 ALU2 ORB, $3 ALU2 ORBC,
|
||||
$4 ALU2 XORB,
|
||||
$8 ALU2 MULL, $a ALU2 MULUH, $b ALU2 MULSH,
|
||||
$c ALU2 QUOU, $d ALU2 QUOS, $e ALU2 REMU, $f ALU2 REMS,
|
||||
|
||||
: BRANCH1 offset8 4 bits ssss tttt o l l l OP ;
|
||||
$0 BRANCH1 BNONE, $1 BRANCH1 BEQ, $2 BRANCH1 BLT, $3 BRANCH1 BLTU,
|
||||
$4 BRANCH1 BALL, $5 BRANCH1 BBC,
|
||||
offset8 o l l b ssss bbbb o l l l OP BBCI,
|
||||
$8 BRANCH1 BANY, $9 BRANCH1 BNE, $a BRANCH1 BGE, $b BRANCH1 BGEU,
|
||||
$c BRANCH1 BNALL, $d BRANCH1 BBS,
|
||||
offset8 l l l b ssss bbbb o l l l OP BBSI,
|
||||
|
||||
: BRANCH2 offset12 ssss 4 bits o l l o OP ;
|
||||
: BRANCH2a offset8 rrrr ssss 4 bits o l l o OP ;
|
||||
: BRANCH2e entry12 ssss 4 bits o l l o OP ;
|
||||
( $0 J, ) $1 BRANCH2 BEQZ, $2 BRANCH2a BEQI, $3 BRANCH2e ENTRY,
|
||||
( $4 J, ) $5 BRANCH2 BNEZ, $6 BRANCH2a BNEI, ( BRANCH2b's )
|
||||
( $8 J, ) $9 BRANCH2 BLTZ, $a BRANCH2a BLTI, $b BRANCH2a BLTUI,
|
||||
( $c J, ) $d BRANCH2 BGEZ, $e BRANCH2a BGEI, $f BRANCH2a BGEUI,
|
||||
offset18 o o o l l o OP J,
|
||||
: BRANCH2b offset8 4 bits ssss o l l l o l l o OP ;
|
||||
$0 BRANCH2b BF, $1 BRANCH2b BT,
|
||||
$8 BRANCH2b LOOP, $9 BRANCH2b LOOPNEZ, $a BRANCH2b LOOPGTZ,
|
||||
|
||||
: CALLOP coffset18 2 bits o l o l OP ;
|
||||
0 CALLOP CALL0, 1 CALLOP CALL4, 2 CALLOP CALL8, 3 CALLOP CALL12,
|
||||
|
||||
: CALLXOP o o o o o o o o o o o o ssss l l 2 bits o o o o OP ;
|
||||
0 CALLXOP CALLX0, 1 CALLXOP CALLX4, 2 CALLXOP CALLX8, 3 CALLXOP CALLX12,
|
||||
|
||||
o o o o o o o o o l o o ssss tttt o o o o OP BREAK,
|
||||
o o l l o o l l rrrr ssss tttt o o o o OP CLAMPS,
|
||||
|
||||
: CACHING1 imm8 o l l l ssss 4 bits o o l o OP ;
|
||||
$0 CACHING1 DPFR, $1 CACHING1 DPFW, $2 CACHING1 DPFRO, $3 CACHING1 DPFWO,
|
||||
$4 CACHING1 DHWB, $5 CACHING1 DHWBI, $6 CACHING1 DHI, $7 CACHING1 DII,
|
||||
( $8 CACHING2 ) ( ?? ) ( ?? ) ( ?? )
|
||||
$c CACHING1 IPF, ( $d CACHING2 ) $e CACHING1 IHI, $f CACHING1 III,
|
||||
|
||||
: CACHING2 imm4 4 bits o l l l ssss 4 bits o o l o OP ;
|
||||
$0 $8 CACHING2 DPFL, $2 $8 CACHING2 DHU, $3 $8 CACHING2 DIU,
|
||||
$4 $8 CACHING2 DIWB, $5 $8 CACHING2 DIWBI,
|
||||
$0 $d CACHING2 IPFL, $2 $d CACHING2 IHU, $3 $d CACHING2 IIU,
|
||||
|
||||
iiii iiii l o l o iiii tttt o o l o OP MOVI,
|
||||
|
||||
: LDSTORE imm8 4 bits ssss tttt o o l o OP ;
|
||||
$0 LDSTORE L8UI, $1 LDSTORE L16UI, $2 LDSTORE L32I, ( $3 CACHING )
|
||||
$4 LDSTORE S8I, $5 LDSTORE S16I, $6 LDSTORE S32I,
|
||||
$9 LDSTORE L16SI, ( $a MOVI ) $b LDSTORE L32AI,
|
||||
$c LDSTORE ADDI, $d LDSTORE ADDMI, $e LDSTORE S32C1I, $f LDSTORE S32RI,
|
||||
|
||||
o l o o l o o l rrrr ssss tttt o o o o OP S32E,
|
||||
|
||||
x x x x o l o sa rrrr sa sa sa sa tttt o o o o OP EXTUI,
|
||||
|
||||
imm16 tttt o o o l OP L32R,
|
||||
l o o l o o o o o o w w ssss o o o o o l o o OP LDDEC,
|
||||
l o o o o o o o o o w w ssss o o o o o l o o OP LDINC,
|
||||
imm8 o o o o ssss tttt o o l l OP LSI,
|
||||
imm8 l o o o ssss tttt o o l l OP LSIU,
|
||||
|
||||
o l o l o o o o l l o o ssss o o o o o o o o OP IDTLB,
|
||||
o l o l o o o o o l o o ssss o o o o o o o o OP IITLB,
|
||||
o o o o o o o o o o o o ssss l o l o o o o o OP JX,
|
||||
l l l l o o o l l o o o ssss tttt o o o o OP LDCT,
|
||||
l l l l o o o l o o o o ssss tttt o o o o OP LICT,
|
||||
l l l l o o o l o o l o ssss tttt o o o o OP LICW,
|
||||
o o o o l o o l rrrr ssss tttt o o o o OP L32E,
|
||||
o o o o l o o o rrrr ssss tttt o o o o OP LSX,
|
||||
o o o l l o o o rrrr ssss tttt o o o o OP LSXU,
|
||||
o o l o o o o o rrrr ssss tttt o o o o OP MOV,
|
||||
|
||||
: CONDOP 4 bits o o l l rrrr ssss tttt o o o o OP ;
|
||||
$4 CONDOP MIN, $5 CONDOP MAX, $6 CONDOP MINU, $7 CONDOP MAXU,
|
||||
$8 CONDOP MOVEQZ, $9 CONDOP MOVNEZ, $a CONDOP MOVLTZ, $b CONDOP MOVGEZ,
|
||||
$c CONDOP MOVF,
|
||||
|
||||
: ALU.S 4 bits l o l o rrrr ssss tttt o o o o OP ;
|
||||
$0 ALU.S ADD.S, $1 ALU.S SUB.S, $2 ALU.S MUL.S,
|
||||
$4 ALU.S MADD.S, $5 ALU.S MSUB.S,
|
||||
$8 ALU.S ROUND.S, $9 ALU.S TRUNC.S, $a ALU.S FLOOR.S, $b ALU.S CEIL.S,
|
||||
$c ALU.S FLOAT.S, $d ALU.S UFLOAT.S, $e ALU.S UTRUNC.S,
|
||||
: ALU2.S l l l l l o l o rrrr ssss 4 bits o o o o OP ;
|
||||
$0 ALU2.S MOV.S, $1 ALU2.S ABS.S,
|
||||
$4 ALU2.S RFR, $5 ALU2.S WFR, $6 ALU2.S NEG.S,
|
||||
|
||||
: CMPSOP 4 bits l o l l rrrr ssss tttt o o o o OP ;
|
||||
$1 CMPSOP UN.S, $2 CMPSOP OEQ.S, $3 CMPSOP UEQ.S,
|
||||
$4 CMPSOP OLT.S, $5 CMPSOP ULT.S, $6 CMPSOP OLE.S, $7 CMPSOP ULE.S,
|
||||
$8 CMPSOP MOVEQZ.S, $9 CMPSOP MOVNEZ.S, $a CMPSOP MOVLTZ.S, $b CMPSOP MOVGEZ.S,
|
||||
$c CMPSOP MOVF.S, $d CMPSOP MOVT.S,
|
||||
|
||||
o o o o o o o o o o o l ssss tttt o o o o OP MOVSP,
|
||||
|
||||
l l o l o o l l rrrr ssss tttt o o o o OP MOVT,
|
||||
: MUL.AA o l l l o l 2 bits o o o o ssss tttt o l o o OP ;
|
||||
0 MUL.AA MUL.AA.LL, 1 MUL.AA MUL.AA.HL, 2 MUL.AA MUL.AA.LH, 3 MUL.AA MUL.AA.HH,
|
||||
: MUL.AD o l l l o l 2 bits o o o o ssss o y o o o l o o OP ;
|
||||
0 MUL.AD MUL.AD.LL, 1 MUL.AD MUL.AD.HL, 2 MUL.AD MUL.AD.LH, 3 MUL.AD MUL.AD.HH,
|
||||
: MUL.DA o l l o o l 2 bits o x o o o o o o tttt o l o o OP ;
|
||||
0 MUL.DA MUL.DA.LL, 1 MUL.DA MUL.DA.HL, 2 MUL.DA MUL.DA.LH, 3 MUL.DA MUL.DA.HH,
|
||||
: MUL.DD o o l o o l 2 bits o x o o o o o o o y o o o l o o OP ;
|
||||
0 MUL.DD MUL.DD.LL, 1 MUL.DD MUL.DD.HL, 2 MUL.DD MUL.DD.LH, 3 MUL.DD MUL.DD.HH,
|
||||
l l o l o o o l rrrr ssss tttt o o o o OP MUL16S,
|
||||
l l o o o o o l rrrr ssss tttt o o o o OP MUL16U,
|
||||
: MULA.AA o l l l l o 2 bits ssss tttt o l o o OP ;
|
||||
0 MULA.AA MULA.AA.LL, 1 MULA.AA MULA.AA.HL, 2 MULA.AA MULA.AA.LH, 3 MULA.AA MULA.AA.HH,
|
||||
: MULA.AD o o l l l o 2 bits ssss tttt o l o o OP ;
|
||||
0 MULA.AD MULA.AD.LL, 1 MULA.AD MULA.AD.HL, 2 MULA.AD MULA.AD.LH, 3 MULA.AD MULA.AD.HH,
|
||||
: MULA.DA o l l o l o 2 bits o x o o o o o o tttt o l o o OP ;
|
||||
0 MULA.DA MULA.DA.LL, 1 MULA.DA MULA.DA.HL, 2 MULA.DA MULA.DA.LH, 3 MULA.DA MULA.DA.HH,
|
||||
: MULA.DA.LDDEC o l o l l o 2 bits o x o o o o o o tttt o l o o OP ;
|
||||
0 MULA.DA.LDDEC MULA.DA.LL.LDDEC, 1 MULA.DA.LDDEC MULA.DA.HL.LDDEC,
|
||||
2 MULA.DA.LDDEC MULA.DA.LH.LDDEC, 3 MULA.DA.LDDEC MULA.DA.HH.LDDEC,
|
||||
: MULA.DA.LDINC o l o o l o 2 bits o x w o o o o o tttt o l o o OP ;
|
||||
0 MULA.DA.LDINC MULA.DA.LL.LDINC, 1 MULA.DA.LDINC MULA.DA.HL.LDINC,
|
||||
2 MULA.DA.LDINC MULA.DA.LH.LDINC, 3 MULA.DA.LDINC MULA.DA.HH.LDINC,
|
||||
: MULA.DD o o l o l o 2 bits o x o o o o o o o y o o o l o o OP ;
|
||||
0 MULA.DD MULA.DD.LL, 1 MULA.DD MULA.DD.HL, 2 MULA.DD MULA.DD.LH, 3 MULA.DD MULA.DD.HH,
|
||||
: MULA.DD.LDDEC o o o l l o 2 bits o x w w o o o o tttt o l o o OP ;
|
||||
0 MULA.DD.LDDEC MULA.DD.LL.LDDEC, 1 MULA.DD.LDDEC MULA.DD.HL.LDDEC,
|
||||
2 MULA.DD.LDDEC MULA.DD.LH.LDDEC, 3 MULA.DD.LDDEC MULA.DD.HH.LDDEC,
|
||||
: MULA.DD.LDINC o o o o l o 2 bits o x w w o o o o tttt o l o o OP ;
|
||||
0 MULA.DD.LDINC MULA.DD.LL.LDINC, 1 MULA.DD.LDINC MULA.DD.HL.LDINC,
|
||||
2 MULA.DD.LDINC MULA.DD.LH.LDINC, 3 MULA.DD.LDINC MULA.DD.HH.LDINC,
|
||||
: MULS.AA o l l l l o 2 bits o o o o ssss tttt o l o o OP ;
|
||||
0 MULS.AA MULA.AA.LL, 1 MULS.AA MULA.AA.HL, 2 MULS.AA MULA.AA.LH, 3 MULS.AA MULA.AA.HH,
|
||||
: MULS.AD o o l l l o 2 bits o o o o ssss o y o o o l o o OP ;
|
||||
0 MULS.AD MULA.AD.LL, 1 MULS.AD MULA.AD.HL, 2 MULS.AD MULA.AD.LH, 3 MULS.AD MULA.AD.HH,
|
||||
: MULS.DA o l l o l o 2 bits o x o o o o o o tttt o l o o OP ;
|
||||
0 MULS.DA MULA.DA.LL, 1 MULS.DA MULA.DA.HL, 2 MULS.DA MULA.DA.LH, 3 MULS.DA MULA.DA.HH,
|
||||
: MULS.DD o o l o l o 2 bits o x o o o o o o o y o o o l o o OP ;
|
||||
0 MULS.DD MULA.DD.LL, 1 MULS.DD MULA.DD.HL, 2 MULS.DD MULA.DD.LH, 3 MULS.DD MULA.DD.HH,
|
||||
|
||||
o l o o o o o o l l l o ssss tttt o o o o OP NSA,
|
||||
o l o o o o o o l l l l ssss tttt o o o o OP NSAU,
|
||||
|
||||
o l o l o o o o l l o l ssss tttt o o o o OP PDTLB,
|
||||
o l o l o o o o o l o l ssss tttt o o o o OP PITLB,
|
||||
o l o l o o o o l o l l ssss tttt o o o o OP RDTLB0,
|
||||
o l o l o o o o l l l l ssss tttt o o o o OP RDTLB1,
|
||||
o l o o o o o o o l l o ssss tttt o o o o OP RER,
|
||||
o l o l o o o o o o l l ssss tttt o o o o OP RITLB0,
|
||||
o l o l o o o o o l l l ssss tttt o o o o OP RITLB1,
|
||||
o l o o o o o o l o o o o o o o imm4 o o o o OP ROTW,
|
||||
o o o o o o o o o o l l imm4 o o o l o o o o OP RFI,
|
||||
o o o o o o o o o l l o imm4 tttt o o o o OP RSIL,
|
||||
o o o o o o l l sr tttt o o o o OP RSR,
|
||||
l l l o o o l l rrrr ssss tttt o o o o OP RUR,
|
||||
l l l l o o o l l o o l ssss tttt o o o o OP SDCT,
|
||||
o o l o o o l l rrrr ssss tttt o o o o OP SEXT,
|
||||
l l l l o o o l o o o l ssss tttt o o o o OP SICT,
|
||||
l l l l o o o l o o l l ssss tttt o o o o OP SICW,
|
||||
l o l o o o o l rrrr ssss o o o o o o o o OP SLL,
|
||||
o o o sa o o o l rrrr ssss sa sa sa sa o o o o OP SLLI,
|
||||
l o l l o o o l rrrr o o o o tttt o o o o OP SRA,
|
||||
o o l x o o o l rrrr xxxx tttt o o o o OP SRAI,
|
||||
l o o o o o o l rrrr ssss tttt o o o o OP SRC,
|
||||
l o o l o o o l rrrr o o o o tttt o o o o OP SRL,
|
||||
o l o o o o o l rrrr xxxx tttt o o o o OP SRLI,
|
||||
o l o o o o o o o o l l ssss o o o o o o o o OP SSA8B,
|
||||
o l o o o o o o o o l o ssss o o o o o o o o OP SSA8L,
|
||||
o l o o o o o o o l o o xxxx o o o x o o o o OP SSAI,
|
||||
imm8 o l o o ssss tttt o o l l OP SSI,
|
||||
imm8 l l o o ssss tttt o o l l OP SSIU,
|
||||
o l o o o o o o o o o l ssss o o o o o o o o OP SSL,
|
||||
o l o o o o o o o o o o ssss o o o o o o o o OP SSR,
|
||||
o l o o l o o o rrrr ssss tttt o o o o OP SSX,
|
||||
o l o l l o o o rrrr ssss tttt o o o o OP SSXU,
|
||||
( TODO: UMUL.AA.* )
|
||||
o o o o o o o o o l l l imm4 o o o o o o o o OP WAITI,
|
||||
o l o l o o o o l l l o ssss tttt o o o o OP WDTLB,
|
||||
o l o o o o o o o l l l ssss tttt o o o o OP WER,
|
||||
o l o l o o o o o l l o ssss tttt o o o o OP WITLB,
|
||||
o o o l o o l l sr tttt o o o o OP WSR,
|
||||
l l l l o o l l sr tttt o o o o OP WUR,
|
||||
|
||||
also forth definitions
|
||||
: xtensa-assembler xtensa ;
|
||||
previous previous
|
||||
xtensa-assembler
|
||||
current !
|
||||
|
||||
| evaluate ;
|
||||
|
||||
[THEN]
|
||||
53
esp32/optional/oled.h
Normal file
53
esp32/optional/oled.h
Normal file
@ -0,0 +1,53 @@
|
||||
// Copyright 2023 Bradley D. Nelson
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*
|
||||
* ESP32forth Assemblers v{{VERSION}}
|
||||
* Revision: {{REVISION}}
|
||||
*/
|
||||
|
||||
// You will need to install these libraries from the Library Manager:
|
||||
// Adafruit SSD1306
|
||||
// Adafruit GFX Library
|
||||
// Adafruit BusIO
|
||||
|
||||
# ifndef SIM_PRINT_ONLY
|
||||
# include <Adafruit_GFX.h>
|
||||
# include <Adafruit_SSD1306.h>
|
||||
static Adafruit_SSD1306 *oled_display = 0;
|
||||
# endif
|
||||
# define OPTIONAL_OLED_SUPPORT \
|
||||
YV(oled, OledAddr, PUSH &oled_display) \
|
||||
YV(oled, OledNew, oled_display = new Adafruit_SSD1306(n2, n1, &Wire, n0); DROPn(3)) \
|
||||
YV(oled, OledDelete, delete oled_display) \
|
||||
YV(oled, OledBegin, n0 = oled_display->begin(n1, n0); NIP) \
|
||||
YV(oled, OledHOME, oled_display->setCursor(0,0); DROP) \
|
||||
YV(oled, OledCLS, oled_display->clearDisplay()) \
|
||||
YV(oled, OledTextc, oled_display->setTextColor(n0); DROP) \
|
||||
YV(oled, OledPrintln, oled_display->println(c0); DROP) \
|
||||
YV(oled, OledNumln, oled_display->println(n0); DROP) \
|
||||
YV(oled, OledNum, oled_display->print(n0); DROP) \
|
||||
YV(oled, OledDisplay, oled_display->display()) \
|
||||
YV(oled, OledPrint, oled_display->write(c0); DROP) \
|
||||
YV(oled, OledInvert, oled_display->invertDisplay(n0); DROP) \
|
||||
YV(oled, OledTextsize, oled_display->setTextSize(n0); DROP) \
|
||||
YV(oled, OledSetCursor, oled_display->setCursor(n1,n0); DROPn(2)) \
|
||||
YV(oled, OledPixel, oled_display->drawPixel(n2, n1, n0); DROPn(2)) \
|
||||
YV(oled, OledDrawL, oled_display->drawLine(n4, n3, n2, n1, n0); DROPn(4)) \
|
||||
YV(oled, OledCirc, oled_display->drawCircle(n3,n2, n1, n0); DROPn(3)) \
|
||||
YV(oled, OledCircF, oled_display->fillCircle(n3, n2, n1, n0); DROPn(3)) \
|
||||
YV(oled, OledRect, oled_display->drawRect(n4, n3, n2, n1, n0); DROPn(4)) \
|
||||
YV(oled, OledRectF, oled_display->fillRect(n4, n3, n2, n1, n0); DROPn(3)) \
|
||||
YV(oled, OledRectR, oled_display->drawRoundRect(n5, n4, n3, n2, n1, n0); DROPn(5)) \
|
||||
YV(oled, OledRectRF, oled_display->fillRoundRect(n5, n4, n3, n2, n1, n0 ); DROPn(5))
|
||||
Reference in New Issue
Block a user