More xtensa assembler improvements.

common/assembler.fs

@@ -86,7 +86,7 @@ variable opcodes
          r@ >pattern
          0 r@ >operands begin dup @ while >r 1+ r> 2 cells + repeat
          swap for aft
-           2 cells - dup >r cell+ @ swap >r enmask r> swap r@ @ >inop execute or r>
+           2 cells - dup >r swap >r dup cell+ @ >r @ >inop execute r> enmask r> or r>
          then next
          drop
          r> >length coden,
@@ -97,8 +97,10 @@ variable opcodes
 
 : m@ ( a -- n ) 0 swap cell 0 do dup ca@ i 8 * lshift swap >r or r> 1+ loop drop ;
 : m. ( n n -- ) base @ hex >r >r <# r> 1- for # # next #> type r> base ! ;
+: sextend ( n n -- n ) cell 8 * swap - dup >r lshift r> arshift ;
 
 variable istep
+variable address
 : matchit ( a xt -- a )
   >r dup m@ r@ >mask and r@ >pattern = if
     r@ >operands begin dup @ while
@@ -108,7 +110,7 @@ variable istep
     r@ >length 8 / istep !
   then rdrop ;
 : disasm1 ( a -- a )
-  dup . ."  --  " 0 istep ! ['] matchit for-ops
+  dup address ! dup . ."  --  " 0 istep ! ['] matchit for-ops
   istep @ 0= if 1 istep ! ." UNKNOWN!!!" then
   9 emit 9 emit ." -- " dup m@ istep @ m.
   istep @ +

esp32/xtensa-assembler.fs

@@ -30,17 +30,33 @@ numeric operand im
 : imm8   imm4 imm4 ;
 : imm12   imm4 imm4 imm4 ;
 : imm16   imm8 imm8 ;
-: offset   imm8 imm8 im im ;
 : sr   imm8 ;
 
+( Offsets for J )
+: >ofs ( n -- n ) chere - 4 - ;
+: ofs. ( n -- ) 18 sextend address @ + 4 + . ;
+' >ofs ' ofs. operand ofs
+: offset   18 for aft ofs then next ;
+
+( Frame size of ENTRY )
+: >entry12 ( n -- n ) 3 rshift ;
+: entry12. ( n -- ) 3 lshift . ;
+' >entry12 ' entry12. operand entry12'
+: entry12   12 for aft entry12' then next ;
+
+: >sa ( n -- n ) 32 swap - ;
+: sa. ( n -- ) 32 swap - . ;
+' >sa ' sa. operand sa
+
+numeric operand x   : xxxx   x x x x ;
+numeric operand i   : iiii   i i i i ;
+numeric operand w
+numeric operand y
+numeric operand b   : bbbb   b b b b ;
+
 register operand r   : rrrr   r r r r ;
 register operand s   : ssss   s s s s ;
 register operand t   : tttt   t t t t ;
-numeric operand i   : iiii   i i i i ;
-numeric operand w
-numeric operand x   : xxxx   x x x x ;
-numeric operand y
-numeric operand b   : bbbb   b b b b ;
 
 imm4     ssss     tttt     l o o o  OP L32I.N,
 imm4     ssss     tttt     l o o l  OP S32I.N,
@@ -107,7 +123,8 @@ imm8  l l l b  ssss  bbbb  o l l l  OP BBSI,
 
 : BRANCH2   imm12  ssss  4 bits  o l l o  OP ;
 : BRANCH2a   imm8  rrrr     ssss  4 bits  o l l o  OP ;
-( $0 J, )  $1 BRANCH2 BEQZ,  $2 BRANCH2a BEQI,  $3 BRANCH2 ENTRY,
+: BRANCH2e   entry12  ssss  4 bits  o l l o  OP ;
+( $0 J, )  $1 BRANCH2 BEQZ,  $2 BRANCH2a BEQI,  $3 BRANCH2e ENTRY,
 ( $4 J, )  $5 BRANCH2 BNEZ,  $6 BRANCH2a BNEI,  ( BRANCH2b's )
 ( $8 J, )  $9 BRANCH2 BLTZ,  $a BRANCH2a BLTI,  $b BRANCH2a BLTUI,
 ( $c J, )  $d BRANCH2 BGEZ,  $e BRANCH2a BGEI,  $f BRANCH2a BGEUI,
@@ -247,7 +264,7 @@ o o l o  o o l l  rrrr  ssss  tttt  o o o o  OP SEXT,
 l l l l  o o o l  o o o l  ssss  tttt  o o o o  OP SICT,
 l l l l  o o o l  o o l l  ssss  tttt  o o o o  OP SICW,
 l o l o  o o o l  rrrr  ssss  o o o o  o o o o  OP SLL,
-o o o x  o o o l  rrrr  ssss  xxxx  o o o o  OP SLLI,
+o o o sa  o o o l  rrrr  ssss  sa sa sa sa  o o o o  OP SLLI,
 l o l l  o o o l  rrrr  o o o o  tttt  o o o o  OP SRA,
 o o l x  o o o l  rrrr  xxxx  tttt  o o o o  OP SRAI,
 l o o o  o o o l  rrrr  ssss  tttt  o o o o  OP SRC,

examples/asm_xtensa.fs

@@ -0,0 +1,28 @@
+#! /usr/bin/env ueforth
+
+\ Copyright 2022 Bradley D. Nelson
+\
+\ Licensed under the Apache License, Version 2.0 (the "License");
+\ you may not use this file except in compliance with the License.
+\ You may obtain a copy of the License at
+\
+\     http://www.apache.org/licenses/LICENSE-2.0
+\
+\ Unless required by applicable law or agreed to in writing, software
+\ distributed under the License is distributed on an "AS IS" BASIS,
+\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+\ See the License for the specific language governing permissions and
+\ limitations under the License.
+
+xtensa-assembler
+
+code my2*
+  a1 32 ENTRY,
+  a8 a2 0 L32I.N,
+  a8 a8 1 SLLI,
+  a8 a2 0 S32I.N,
+  RETW.N,
+end-code
+
+' my2* cell+ @ 20 disasm
+bye